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Automated Offline Design-Space Exploration and Online Design Reconfiguration for CNNs

Mazouz, A. and Bridges, C.P (2020) Automated Offline Design-Space Exploration and Online Design Reconfiguration for CNNs In: 2020 IEEE Conference on Evolving and Adaptive Intelligent Systems (EAIS), 27-29 May 2020, Bari, Italy.

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In this work, we propose a design space exploration workflow and tool for generating reconfigurable deep learning hardware models for FPGAs. The workflow is broken down into two main parts, Offline Design Exploration (ODE) and Online Design Reconfiguration (ODR). Offline Design Exploration is automated through a workflow methodology which makes it possible for a designer to provide a Convolutional Neural Network (CNN) architecture and the option of providing additional design constraints in terms of latency and space. These automatically generate multiple design spaces which trade-off latency for resource utilization by dedicating varying processing elements through loop reordering, unrolling and pipelining. The second part of the process introduces online reconfiguration to the design space. Online Reconfiguration means the ability to modify the design at runtime after upload, by selectively running it partially or fully according to an application’s immediate requirements, this provides the design with flexibility which, we believe, is highly beneficial for future autonomous on-board applications. We validate our work on the Xilinx Zynq-7100 board at 200 MHz and use custom trained networks architectures on three datasets for image classification, MNIST, SVHN and CIFAR-10. ODE generated designs achieved latency trade-offs of 95x for MNIST, 71x for CIFAR-10 and 18x for SVHN. Trade-offs in resource utilization in terms of DSP Slices were 44x for MNIST, 52x for SVHN and 24x for CIFAR-10. For the ODR, a 0.7% accuracy loss was traded-off with x13 speedup and a 25% reduction in power for MNIST, a 2% accuracy loss was traded-off with a 14x speedup and a 28% power reduction for SVHN, a 4% accuracy loss was traded off for a 50x speedup with 32.5% power reduction for CIFAR-10.

Item Type: Conference or Workshop Item (Conference Paper)
Divisions : Faculty of Engineering and Physical Sciences > Electronic Engineering
Authors :
Mazouz, A.
Date : 23 June 2020
DOI : 10.1109/EAIS48028.2020.9122697
Copyright Disclaimer : © 2020 IEEE
Depositing User : James Marshall
Date Deposited : 30 Jun 2020 09:58
Last Modified : 30 Jun 2020 10:03

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