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Fault Tolerance of On-Board Processors for Communication Satellites.

Raghunandan, K. (1991) Fault Tolerance of On-Board Processors for Communication Satellites. Doctoral thesis, University of Surrey (United Kingdom)..

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This thesis is concerned with an industrial problem related to fault tolerance, on board satellites. At present, faults on-board satellites are recognised by human controllers at ground stations, who receive signals through telemetry channels. They correlate these signals with fault models, analyse them and then send back commands to the satellite, in an attempt to correct the situation. This task can take half a day to several days. Instead, if an autonomous fault tolerance system is provided on-board, this task could be accomplished in a matter of seconds (typically 5 seconds). This work attempts to provide such an autonomous fault tolerance system, for the on-board processor to be used in future communication satellites. The thesis begins with an emphasis on the need for fault-tolerance in satellite communication systems to achieve high reliability and uninterrupted operation. With a brief review of satellite technology, the advantages of On-Board Processing (OBP) in the satellite communications system are outlined and the limitations of providing reliable service with the current configuration are described. Since the concept of OBP in communication satellites is relatively new, a review of satellite communication describes the limitations of existing technology and highlights the role of Digital Signal Processing (DSP) in OBP. An overview of the fault tolerance methods describes the differences between the techniques used for mainframe computers and DSP. The techniques available for DSP circuits are reviewed, since OBP uses digital filters as its Processing Elements (PEs). An important element of the OBP, known as a Digital Channeliser (DCH) is chosen as the target system for which fault tolerance techniques are developed in this thesis. A to D Converters (ADCs), which are needed to convert analog signals into the digital domain of a DCH, have limitations in terms of fault detection since its input and output are in different domains, making a direct comparison difficult. However, test methods to characterise errors in ADCs are well developed and these are examined to evolve a procedure for fault simulation of the on-board ADCs. Simulation results indicate that the bit length of ADCs can be reduced, for fault detection in real-time. Multipliers are perhaps the most important elements in all DSP circuits, including the DCH. Fault detection schemes currently available for multipliers are based on specific configurations of the multiplier hardware and these schemes do not offer real-time error detection. A novel software based space search scheme is developed in this thesis to overcome these limitations and extended to the other functional elements of a digital filter. The new space search scheme not only needs a smaller hardware count for implementation, but also provides a universal method to detect errors in real-time in all configurations of two's complement multipliers. A Programmable Logic Array (PLA) is used to implement the space search scheme onboard. The PLA is used to check for errors in the multiplier and other elements in real-time; it is provided with a self-check facility, which enhances the confidence in the checking process. Multiplexers and Adders/Subtractors are extensively used in DSP circuits. Error detection in such operators may also be achieved by an extension of the new space search method. Techniques of software fault-tolerance such as data diversity, are applied to provide an effective means of error detection in real-time. The algorithms for error detection are developed using an AI programming language called Prolog, whose inherent capabilities are used to provide a simple approach in order to detect errors in real-time on-board circuits such as the DCH. The DCH is implemented as a time-multiplexed binary tree structure. Reconfiguration techniques currently available for binary tree structures are based on modular schemes but need many redundant Processing Elements (PEs). A new Serial-Module (SM) scheme for a time-multiplexed binary tree is developed so as to reduce the number of redundant PEs but at the same time to improve the reliability of DCH. The DCH is an on-board system and its diagnostics requirements at the sub-system and system level are outlined. An existing diagnostics system is used to integrate the error detection schemes evolved in this thesis and provide fault tolerance to the DCH. Concluding remarks on the features of fault-tolerant schemes developed are highlighted and the scope for further work in this new and promising area of "autonomous fault-tolerant communication system" is outlined. FEATURES A comprehensive scheme for fault tolerance in satellite communication sub-system is developed using the DCH as a candidate. The techniques proposed for fault tolerance in a DCH are suitable for real-time implementation in communication satellites without much increase in hardware or software complexity. The methods developed in this thesis can be extended to other DSP circuits in other satellites, since these are general (universal) in nature.

Item Type: Thesis (Doctoral)
Divisions : Theses
Authors : Raghunandan, K.
Date : 1991
Additional Information : Thesis (M.Phil.)--University of Surrey (United Kingdom), 1991.
Depositing User : EPrints Services
Date Deposited : 30 Apr 2019 08:08
Last Modified : 20 Aug 2019 15:33

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