Tolerating memory latency through lightweight multithreading.

Gale, Andrew. (2002) Tolerating memory latency through lightweight multithreading. Doctoral thesis, University of Surrey (United Kingdom)..

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Abstract

As processor clock frequencies continue to improve at a rate that exceeds the rate of improvement in the performance of semiconductor memories, so the effect of memory latency on processor efficiency increases. Unless steps are taken to mitigate the effect of memory latency, the increased processor frequency is of little benefit. This work demonstrates how multithreading can reduce the effect of memory latency on processor performance and how just a few threads are required to achieve close to optimal performance. A lightweight multithreaded architecture is discussed and simulated to show how threads derived from an application's instruction-level parallelism may be used to tolerate memory latency.

Item Type:	Thesis (Doctoral)
Divisions :	Theses
Authors :	Name Email ORCID Gale, Andrew.
Date :	2002
Contributors :	Contribution Name Email ORCID http://www.loc.gov/loc.terms/relators/THS
Depositing User :	EPrints Services
Date Deposited :	09 Nov 2017 12:12
Last Modified :	16 Mar 2018 16:22
URI:	http://epubs.surrey.ac.uk/id/eprint/842940

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