Hardware-in-loop simulation of a satellite sensor network for distributed space applications

Wu, XF and Vladimirova, T (2008) Hardware-in-loop simulation of a satellite sensor network for distributed space applications In: 3rd NASA/ESA Conference on Adaptive Hardware and Systems, 2008-06-22 - 2008-06-25, Noordwijk, NETHERLANDS.

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Abstract

In this paper a hardware-in-loop simulator is presented to demonstrate the satellite sensor network concept developed at the Surrey Space Centre under the ESPACENET project. The simulator includes software that emulates satellite orbit dynamics in Low Earth Orbit and picosatellite sensor nodes. The picosatellite currently under development is based on the CubeSat platform. The main payload will be an FPGA board that implements intellectual property cores like the LEON3 processor, a media access controller for intersatellite links, image compression, encryption, etc.. The payloads of the individual satellites are connected together via IEEE 802.11 intersatellite links to demonstrate a distributed computing plaform for future space missions.

Item Type:	Conference or Workshop Item (UNSPECIFIED)
Divisions :	Surrey research (other units)
Authors :	Name Email ORCID Wu, XF Vladimirova, T t.vladimirova@surrey.ac.uk
Date :	2008
Contributors :	Contribution Name Email ORCID Keymeulen, D Arslan, T Seuss, M Stoica, A Erdogan, AT Merodio, D publisher IEEE COMPUTER SOC,
Uncontrolled Keywords :	distributed computing, FPGA, hardware-in-loop, inter-satellite link, satellite sensor network
Depositing User :	Symplectic Elements
Date Deposited :	17 May 2017 11:18
Last Modified :	23 Jan 2020 16:42
URI:	http://epubs.surrey.ac.uk/id/eprint/830853

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