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Number of items: 15.

Sporea, RA, Shannon, JM, Silva, SRP, Trainor, M and Young, N (2015) Temperature effects in complementary inverters made with polysilicon source-gated transistors IEEE Transactions on Electron Devices, 62 (5). pp. 1498-1503.

Cui, Q, Liu, W, Guo, X and Sporea, RA (2014) Analytical models for delay and power analysis of zero-V load unipolar thin-film Transistor Logic Circuits IEEE Transactions on Electron Devices, 61 (11). pp. 3838-3844.

Shannon, JM, Sporea, RA, Georgakopoulos, S, Shkunov, M and Silva, SRP (2013) Low-Field Behavior of Source-Gated Transistors IEEE Transactions on Electron Devices, 60 (8). pp. 2444-2449.

Shannon, JM, Sporea, RA, Georgakopoulos, S, Shkunov, M and Silva, SRP (2013) Low-Field Behavior of Source-Gated Transistors IEEE Transactions on Electron Devices, 60 (8). pp. 2444-2449.

Shannon, JM, Sporea, RA, Georgakopoulos, S, Shkunov, M and Silva, SRP (2013) Low-Field Behavior of Source-Gated Transistors IEEE Transactions on Electron Devices.

Sporea, RA, Trainor, MJ, Young, ND, Shannon, JM and Silva, SRP (2012) Field plate optimization in low-power high-gain source-gated transistors IEEE Transactions on Electron Devices, 59 (8).

Sporea, RA, Shannon, JM, Silva, SRP, Trainor, MJ and Young, ND (2012) Field plate optimization in low-power high-gain source-gated transistors IEEE Transactions on Electron Devices, 59 (8). pp. 2180-2186.

Sporea, RA, Trainor, MJ, Young, ND, Shannon, JM and Silva, SRP (2010) Intrinsic gain in self-aligned polysilicon source-gated transistors IEEE Transactions on Electron Devices, 57 (10). pp. 2434-2439.

Tan, HT, Hunter, IC and Snowden, CM (2007) Simulation and design of AlGaAs/InGaAs CCDs based on PHEMT technology IEEE Transactions on Electron Devices, 54 (7). pp. 1597-1604.

Shannon, J M and Balon, F (2007) High-Performance Thin-Film Transistors in Disordered and Poor-Quality Semiconductors IEEE Transactions on Electron Devices, 54 (2).

Bain, M., El Mubarek, A. W., Bonar, J. M., Wang, Y., Buiu, O., Gamble, H., Armstrong, B. M., Hemment, P. L. F., Hall, Steven and Ashburn, Peter (2005) SiGe HBTs on bonded SOI incorporating buried silicide layers IEEE Transactions on Electron Devices. pp. 317-324.

El Mubarek, H A, Karunaratne, M, Bonar, J M, Dilliway, G D, Wang, Y, Hemment, P L, Willoughby, A F and Ashburn, P (2005) Effect of Fluorine Implantation Dose on Boron Transient Enhanced Diffusion and Boron Thermal Diffusion in S1-xGex IEEE Transactions on Electron Devices, 52 (4).

Bain, M, El Mubarek, H A, Bonar, J M, Wang, Y, Buiu, O, Gamble, H, Armstrong, B M, Hemment, P L, Hall, S and Ashburn, P (2005) SiGeHBTs on Bonded SOI Incorporating Buried Silicide Layers IEEE Transactions on Electron Devices, 52 (3).

Kunz, V. Dominik, Uchino, Takashi, De Groot, C. H. (Kees), Ashburn, Peter, Donaghy, David C., Hall, Steven, Wang, Yun and Hemment, P. L. F. (2003) Reduction of parasitic capacitance in vertical MOSFETs by spacer local oxidation IEEE Transactions on Electron Devices. pp. 1487-1493.

Schiz, J. F. W., Lamb, Andrew C., Cristiano, Fuccio, Bonar, J. M., Ashburn, Peter, Hall, Stephen and Hemment, P. L. F. (2001) Leakage current mechanisms in SiGe HBTs fabricated using selective and nonselective epitaxy IEEE Transactions on Electron Devices. pp. 2492-2499.

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