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Simulation study of overlap capacitance in source-gated transistors for current-mode pixel drivers

Drury, Raymond, Bestelink, Eva and Sporea, Radu A. (2019) Simulation study of overlap capacitance in source-gated transistors for current-mode pixel drivers IEEE Electron Device Letters.

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Abstract

Contrary to conventional design principles, currentdriven pixel drivers based on source-gated transistors (SGTs) achieve their optimal drive current and speed with a deliberate 5 -10μm gate-source overlap. Total pixel circuit area need not increase, as the additional device area can be compensated by reducing the pixel storage capacitor. Numerical simulations demonstrate the viability of SGTs for emissive pixel drivers and high gain, low power, robust circuits for emerging sensor arrays.

Item Type: Article
Divisions : Faculty of Engineering and Physical Sciences > Electronic Engineering
Authors :
NameEmailORCID
Drury, Raymond
Bestelink, Evae.bestelink@surrey.ac.uk
Sporea, Radu A.R.A.Sporea@surrey.ac.uk
Date : 2 July 2019
DOI : 10.1109/LED.2019.2926351
Copyright Disclaimer : © 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Uncontrolled Keywords : TFT; OLED; Active matrix; Display; Schottky barrier; Pixel circuit; Energy efficiency; Layout optimization
Depositing User : Clive Harris
Date Deposited : 22 Jul 2019 07:32
Last Modified : 22 Jul 2019 07:32
URI: http://epubs.surrey.ac.uk/id/eprint/852283

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