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Single event mitigation for Xilinx 7-series FPGAs

Bates, T and Bridges, Christopher (2018) Single event mitigation for Xilinx 7-series FPGAs In: 2018 IEEE Aerospace Conference, 3 - 10 March 2018, Big Sky, MT, USA.

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This study establishes the optimal Single Event Upset (SEU) mitigation strategy for Xilinx's 7-Series Field Programmable Gate Arrays (FPGAs). This enables 7-Series FPGAs to be utilised in systems with high exposure to ionising radiation over Xilinx's smaller, radiation-hardened 4-Series and 5-Series FPGAs. The optimal strategy maximises system up-time, with minimal complexity and minimal risk of damaging the target FPGA device. Four SEU mitigation techniques are analysed and compared. Three of these are external scrubbing techniques; blind, readback, and blind with Frame Address Register (FAR) verification; with the fourth being Xilinx's internal scrubber, the Soft Error Mitigation (SEM) Intellectual Property (IP) core. The initial comparisons are quantitative, comparing the four methods for traits that lend themselves to meeting the criteria of the optimal scrubber. The techniques are then compared quantitatively to establish theoretical whole-device scan times for each technique given a range of errors to be corrected. These scan times can be utilised to determine which technique performs the fastest given the error rate and technique parameters. The calculations and resultant data can be computed for every device in the 7-series range. The findings suggest that the optimal solution is to opt not for a traditional mitigation strategy, but for a dynamic mitigation strategy. The fastest scrubber is the SEM IP Core, predominantly due to being internal to the FPGA, and as error rates increase, there becomes a crossover point whereby the blind scrubber with FAR verification comes into play to scrub at higher error rates in a deterministic way. Additionally, it finds that the configuration scrubber can operate at higher frequencies in comparison to NASAs recommendation of scrubbing at an order of magnitude higher than the expected SEU rate. These results provide the optimal scrubber for the 7-Series FPGA, and bring into question the recommendation of scrubbing at a higher order of magnitude than the expected error rate. Additionally, Xilinx's guidance for their FPGAs brings in an essential bit ratio which determines what proportion of the FPGAs is actually being utilised by the design, thereby decreasing the proportion of the errors that impact the design as opposed to empty areas of the FPGA, and hence increasing the speed at which scrubbing can take place with reference to NASAs recommendation.

Item Type: Conference or Workshop Item (Conference Paper)
Divisions : Faculty of Engineering and Physical Sciences > Electronic Engineering
Authors :
Bates, T
Date : 28 June 2018
DOI : 10.1109/AERO.2018.8396520
Related URLs :
Depositing User : Melanie Hughes
Date Deposited : 21 Sep 2018 11:10
Last Modified : 21 Sep 2018 11:10

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