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An Efficient Hardware Architecture for Multilayer Spiking Neural Networks

Luo, Yuling, Wan, Lei, Liu, Junxiu and Cao, Yi (2017) An Efficient Hardware Architecture for Multilayer Spiking Neural Networks In: The 24th International Conference on Neural Information Processing (ICONIP 2017), 14-18 Nov 2017, Guanzhou, China.

An Efficient Hardware Architecture for Multilayer Spiking Neural Networks.pdf - Accepted version Manuscript

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Spiking Neural Network (SNN) is the most recent computa tional model that can emulate the behaviors of biological neuron system. This paper highlights and discusses an efficient hardware architecture for the hardware SNNs, which includes a layer-level tile architecture (LTA) for the neurons and synapses, and a novel routing architecture (NRA) for the interconnections between the neuron nodes. In addition, a visu alization performance monitoring platform is designed, which is used as functional verification and performance monitoring for the SNN hard ware system. Experimental results demonstrate that the proposed archi tecture is feasible and capable of scaling to large hardware multilayer SNNs.

Item Type: Conference or Workshop Item (Conference Paper)
Divisions : Faculty of Arts and Social Sciences > Surrey Business School
Authors :
Luo, Yuling
Wan, Lei
Liu, Junxiu
Date : 18 November 2017
DOI : 10.1007/978-3-319-70090-8_83
Copyright Disclaimer : © Springer International Publishing AG 2017
Uncontrolled Keywords : Spiking neural networks; Hardware architecture; FPGA
Related URLs :
Depositing User : Clive Harris
Date Deposited : 19 Sep 2017 15:03
Last Modified : 14 Feb 2018 11:08

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