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Performance evaluation and design guidelines of sub-100-nm source/drain unilateral-crystallized poly-Si TFTs for SoP applications

Guo, X, Adikaari, AADT and Silva, SRP (2006) Performance evaluation and design guidelines of sub-100-nm source/drain unilateral-crystallized poly-Si TFTs for SoP applications In: 13th International Display Workshop (IDW 06), 2006-12-06 - 2006-12-08, Otsu, JAPAN.

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Abstract

The thickness spatial modulation method can realize high-performance source/drain unilateral-crystallized (SDUC) poly-Si thin-film transistors (TFTs). The resulted thick source/drain, un-doped thin-channel device structure is also very promising for ultra-scaled device design. With a calibrated simulation model, the performance and process sensitivity of sub-100-nm SDUC TFTs were predicted by numerical simulations. The results indicate the manufacturability of the devices and highlight guidelines of optimizing the devices for different requirements of low-power or high-performance applications.

Item Type: Conference or Workshop Item (UNSPECIFIED)
Authors :
NameEmailORCID
Guo, XUNSPECIFIEDUNSPECIFIED
Adikaari, AADTUNSPECIFIEDUNSPECIFIED
Silva, SRPs.silva@surrey.ac.ukUNSPECIFIED
Date : 2006
Contributors :
ContributionNameEmailORCID
publisherINST IMAGE INFORMATION & TELEVISION ENGINEERS, UNSPECIFIEDUNSPECIFIED
Uncontrolled Keywords : POLYCRYSTALLINE-SILICON, CHANNEL, FILM
Depositing User : Symplectic Elements
Date Deposited : 17 May 2017 10:58
Last Modified : 17 May 2017 14:53
URI: http://epubs.surrey.ac.uk/id/eprint/829484

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