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Interface Passivation and Trap Reduction via a Solution-Based Method for Near-Zero Hysteresis Nanowire Field-Effect Transistors

Constantinou, M, Stolojan, V, Rajeev, KP, Hinder, S, Fisher, B, Bogart, TD, Korgel, BA and Shkunov, M (2015) Interface Passivation and Trap Reduction via a Solution-Based Method for Near-Zero Hysteresis Nanowire Field-Effect Transistors ACS APPLIED MATERIALS & INTERFACES, 7 (40). pp. 22115-22120.

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Abstract

In this letter, we demonstrate a solution-based method for a one-step deposition and surface passivation of the as-grown silicon nanowires (Si NWs). Using N,N-dimethylformamide (DMF) as a mild oxidizing agent, the NWs' surface traps density was reduced by over 2 orders of magnitude from 1×10(13) cm(-2) in pristine NWs to 3.7×10(10) cm(-2) in DMF-treated NWs, leading to a dramatic hysteresis reduction in NW field-effect transistors (FETs) from up to 32 V to a near-zero hysteresis. The change of the polyphenylsilane NW shell stoichiometric composition was confirmed by X-ray photoelectron spectroscopy analysis showing a 35% increase in fully oxidized Si4+ species for DMF-treated NWs compared to dry NW powder. Additionally, a shell oxidation effect induced by DMF resulted is a more stable NW FET performance with steady transistor currents and only 1.5 V hysteresis after 1000 h of air exposure

Item Type: Article
Subjects : Electronic Engineering
Authors :
AuthorsEmailORCID
Constantinou, MUNSPECIFIEDUNSPECIFIED
Stolojan, VUNSPECIFIEDUNSPECIFIED
Rajeev, KPUNSPECIFIEDUNSPECIFIED
Hinder, SUNSPECIFIEDUNSPECIFIED
Fisher, BUNSPECIFIEDUNSPECIFIED
Bogart, TDUNSPECIFIEDUNSPECIFIED
Korgel, BAUNSPECIFIEDUNSPECIFIED
Shkunov, MUNSPECIFIEDUNSPECIFIED
Date : 14 October 2015
Identification Number : 10.1021/acsami.5b07140
Copyright Disclaimer : Copyright 2015 American Chemical Society.
Uncontrolled Keywords : Science & Technology, Technology, Nanoscience & Nanotechnology, Materials Science, Multidisciplinary, Science & Technology - Other Topics, Materials Science, hysteresis, silicon nanowires, field-effect transistor, nanowire interface, DMF, XPS, interface trap reduction, interface passivation, SILICON NANOWIRES, SEMICONDUCTOR NANOWIRES, TEMPERATURE, NANOSENSORS, OXIDATION, SENSORS, SI
Related URLs :
Depositing User : Symplectic Elements
Date Deposited : 21 Apr 2016 10:04
Last Modified : 14 Oct 2016 01:08
URI: http://epubs.surrey.ac.uk/id/eprint/810280

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