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Analytical models for delay and power analysis of zero-V load unipolar thin-film Transistor Logic Circuits

Cui, Q, Liu, W, Guo, X and Sporea, RA (2014) Analytical models for delay and power analysis of zero-V load unipolar thin-film Transistor Logic Circuits IEEE Transactions on Electron Devices, 61 (11). pp. 3838-3844.

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Abstract

In thin-film transistor (TFT) logic circuit applications, propagation delay and power dissipation are two key constraints to be considered in optimal circuit design and synthesis. The unipolar zero-V-load logic design is widely used for implementation of TFT digital circuits, because of the simple structure, easy processing, and relatively high gain. In this paper, the analytical models for delay and power were developed for zero-V-load inverters, which clarify the relationships between device and design parameters and the two key design constraints. The proposed models were verified by circuit simulations, and could serve as a guideline for optimal design of unipolar zero-V-load logic circuits.

Item Type: Article
Divisions : Faculty of Engineering and Physical Sciences > Electronic Engineering > Advanced Technology Institute > Nano-Electronics Centre
Authors :
AuthorsEmailORCID
Cui, QUNSPECIFIEDUNSPECIFIED
Liu, WUNSPECIFIEDUNSPECIFIED
Guo, XUNSPECIFIEDUNSPECIFIED
Sporea, RAUNSPECIFIEDUNSPECIFIED
Date : 1 November 2014
Identification Number : 10.1109/TED.2014.2353651
Additional Information : © 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Depositing User : Symplectic Elements
Date Deposited : 02 Dec 2014 14:49
Last Modified : 02 Dec 2014 14:49
URI: http://epubs.surrey.ac.uk/id/eprint/806768

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