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Thermal resistance modeling for the electrothermal layout of high-power RF transistors

Aaen, PH, Wood, J, Li, Q and Mares, E (2010) Thermal resistance modeling for the electrothermal layout of high-power RF transistors IEEE MTT-S International Microwave Symposium Digest. pp. 1672-1675.

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This paper demonstrates a practical approach to developing a geometrically scalable thermal resistance model to optimize layout for improved electrical performance of highpower RF transistors. The model is developed using finite element-based simulations, which show very good agreement with measured results. The proposed modeling methodology precomputes simulations over all possible layout considerations and the individual elements of the thermal resistance matrices are automatically approximated by thin-plate splines. This approach produces a model for use within a circuit simulator with virtually no overhead. We are able to scale the model up to 60 mm with less than than 2% error in the maximum predicted temperature rise. © 2010 IEEE.

Item Type: Article
Divisions : Faculty of Engineering and Physical Sciences > Electronic Engineering > Advanced Technology Institute
Authors :
Aaen, PH
Wood, J
Li, Q
Mares, E
Date : 2010
DOI : 10.1109/MWSYM.2010.5518198
Contributors :
Additional Information : © 2010 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Depositing User : Symplectic Elements
Date Deposited : 23 Sep 2013 13:05
Last Modified : 31 Oct 2017 15:14

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