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Simple Noise Margin Model for Optimal Design of Unipolar Thin-Film Transistor Logic Circuits

Cui, Q, Si, M, Sporea, RA and Guo, X (2013) Simple Noise Margin Model for Optimal Design of Unipolar Thin-Film Transistor Logic Circuits IEEE TRANSACTIONS ON ELECTRON DEVICES, 60 (5). pp. 1782-1785.

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Item Type: Article
Divisions : Faculty of Engineering and Physical Sciences > Electronic Engineering > Advanced Technology Institute > Nano-Electronics Centre
Authors :
AuthorsEmailORCID
Cui, QUNSPECIFIEDUNSPECIFIED
Si, MUNSPECIFIEDUNSPECIFIED
Sporea, RAUNSPECIFIEDUNSPECIFIED
Guo, XUNSPECIFIEDUNSPECIFIED
Date : 1 May 2013
Identification Number : 10.1109/TED.2013.2251346
Uncontrolled Keywords : Science & Technology, Technology, Physical Sciences, Engineering, Electrical & Electronic, Physics, Applied, Engineering, Physics, ENGINEERING, ELECTRICAL & ELECTRONIC, PHYSICS, APPLIED, Noise margin (NM), thin-film transistor (TFT), zero-V-GS load inverter
Related URLs :
Additional Information : © 2013 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Depositing User : Symplectic Elements
Date Deposited : 24 Jul 2013 17:42
Last Modified : 17 Jan 2015 14:38
URI: http://epubs.surrey.ac.uk/id/eprint/789395

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