Performance trade-offs in polysilicon source-gated transistors
Sporea, RA, Trainor, MJ, Young, ND, Guo, X, Shannon, JM and Silva, SRP (2011) Performance trade-offs in polysilicon source-gated transistors Solid-State Electronics, 65-66 (1). pp. 246-249.
SSE ESSDERC 4086 2010 Sporea corrected Symplectic.pdf - Accepted version Manuscript
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Plain Text (licence)
Self-aligned Schottky-source source-gated transistors (SGTs) have been made in polysilicon. The structures enable a direct comparison to be made between a SGT and a standard thin-film field-effect transistor (FET) on the same device. SGTs having excellent characteristics have been fabricated, with intrinsic gains approaching 10,000. The effects of bulk doping in the polysilicon and of the source barrier modification implant are considered in the context of the electrical output characteristics. It is shown that the choice of source length is a tradeoff between device speed and variations in current output due to variability during fabrication.
|Divisions :||Faculty of Engineering and Physical Sciences > Electronic Engineering > Advanced Technology Institute > Nano-Electronics Centre|
|Identification Number :||10.1016/j.sse.2011.06.010|
|Additional Information :||NOTICE: this is the author’s version of a work that was accepted for publication in Solid-State Electronics. Changes resulting from the publishing process, such as peer review, editing, corrections, structural formatting, and other quality control mechanisms may not be reflected in this document. Changes may have been made to this work since it was submitted for publication. A definitive version was subsequently published in Solid-State Electronics, 65-66(1), November-December 2011, DOI 10.1016/j.sse.2011.06.010.|
|Depositing User :||Symplectic Elements|
|Date Deposited :||03 May 2012 13:20|
|Last Modified :||23 Sep 2013 18:52|
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