Performance trade-offs in polysilicon source-gated transistors

Sporea, RA, Shannon, JM, Silva, SRP, Trainor, MJ and Young, ND (2010) Performance trade-offs in polysilicon source-gated transistors Proceedings of the European Solid State Device Research Conference, ESSDERC 2010. pp. 222-225.

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Abstract

Self-aligned Schottky-source source-gated transistors (SGTs) have been made in polysilicon. The structures enable a direct comparison to be made between a SGT and a standard thin-film field-effect transistor (FET) on the same device. SGTs having excellent characteristics have been fabricated, with intrinsic gains approaching 10,000. The effects of bulk doping in the polysilicon and of the source barrier modification implant are considered in the context of the electrical output characteristics. It is shown that the choice of source length is a tradeoff between device speed and current uniformity.

Item Type:	Article
Divisions :	Faculty of Engineering and Physical Sciences > Electronic Engineering > Advanced Technology Institute > Nano-Electronics Centre
Authors :	Name Email ORCID Sporea, RA UNSPECIFIED UNSPECIFIED Shannon, JM UNSPECIFIED UNSPECIFIED Silva, SRP UNSPECIFIED UNSPECIFIED Trainor, MJ UNSPECIFIED UNSPECIFIED Young, ND UNSPECIFIED UNSPECIFIED
Date :	2010
Identification Number :	https://doi.org/10.1109/ESSDERC.2010.5618382
Contributors :	Contribution Name Email ORCID http://www.loc.gov/loc.terms/relators/PBL IEEE, UNSPECIFIED UNSPECIFIED
Additional Information :	Copyright 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Depositing User :	Symplectic Elements
Date Deposited :	06 Feb 2012 10:30
Last Modified :	09 Jun 2014 13:22
URI:	http://epubs.surrey.ac.uk/id/eprint/7848

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