Performance trade-offs in polysilicon source-gated transistors
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Sporea, RA, Shannon, JM, Silva, SRP, Trainor, MJ and Young, ND (2010) Performance trade-offs in polysilicon source-gated transistors In: European Solid-State Device Research Conference (ESSDERC), 2010-09-14 - 2010-09-16, Sevilla, Spain.
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Official URL: http://dx.doi.org/10.1109/ESSDERC.2010.5618382
Abstract
Self-aligned Schottky-source source-gated transistors (SGTs) have been made in polysilicon. The structures enable a direct comparison to be made between a SGT and a standard thin-film field-effect transistor (FET) on the same device. SGTs having excellent characteristics have been fabricated, with intrinsic gains approaching 10,000. The effects of bulk doping in the polysilicon and of the source barrier modification implant are considered in the context of the electrical output characteristics. It is shown that the choice of source length is a tradeoff between device speed and current uniformity.
| Item Type: | Conference or Workshop Item (UNSPECIFIED) | ||||||||
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| Divisions : | Faculty of Engineering and Physical Sciences > Electronic Engineering > Advanced Technology Institute > Nano-Electronics Centre | ||||||||
| Authors : | Sporea, RA, Shannon, JM, Silva, SRP, Trainor, MJ and Young, ND | ||||||||
| Date : | 2010 | ||||||||
| DOI : | 10.1109/ESSDERC.2010.5618382 | ||||||||
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| Additional Information : |
Copyright 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. |
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| Depositing User : | Symplectic Elements | ||||||||
| Date Deposited : | 06 Feb 2012 10:30 | ||||||||
| Last Modified : | 06 Apr 2020 13:19 | ||||||||
| URI: | http://epubs.surrey.ac.uk/id/eprint/7848 |
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