Performance trade-offs in polysilicon source-gated transistors
Sporea, RA, Trainor, MJ, Young, ND, Guo, X, Shannon, JM and Silva, SRP (2011) Performance trade-offs in polysilicon source-gated transistors Solid-State Electronics, 65-66 (1). pp. 246-249.
SSE ESSDERC 4086 2010 Sporea corrected Symplectic.pdf - Accepted version Manuscript
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|Divisions :||Faculty of Engineering and Physical Sciences > Electronic Engineering > Advanced Technology Institute > Nano-Electronics Centre|
|Additional Information :||NOTICE: this is the author’s version of a work that was accepted for publication in Solid-State Electronics. Changes resulting from the publishing process, such as peer review, editing, corrections, structural formatting, and other quality control mechanisms may not be reflected in this document. Changes may have been made to this work since it was submitted for publication. A definitive version was subsequently published in Solid-State Electronics, 65-66(1), December 2011, DOI 10.1016/j.sse.2011.06.010.|
|Depositing User :||Symplectic Elements|
|Date Deposited :||01 Feb 2012 15:41|
|Last Modified :||23 Sep 2013 18:52|
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