Down-scaling of thin-film transistors: Opportunities and design challenges
Guo, X, Sporea, R, Shannon, JM and Silva, SRP (2009) Down-scaling of thin-film transistors: Opportunities and design challenges ECS Transactions, 22 (1). pp. 227-238.
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With the ever-increasing demands for integration of advanced electronic functions into large-area electronics, down-scaling of thin-film transistors (TFTs) becomes very necessary. The key device operational issues associated with TFT scaling, including short-channel effects (SCEs) and self-heating, are considered in this paper. Device structure engineering approaches are introduced to suppress the SCEs for designing short-channel TFTs with excellent digital and analog performance. And electro-thermal simulation results show that the self-heating in TFTs will be much more significant than that in silicon metal-oxide-semiconductor field-effect transistors (MOSFETs) due to the substrate of poor thermal conductivity. Enhancing the heat dissipation by placement of metal heat pipe in the cap dielectric layers is proved to be an effective way to deal with the heating issues.
|Divisions :||Faculty of Engineering and Physical Sciences > Electronic Engineering > Advanced Technology Institute|
|Identification Number :||10.1149/1.3152980|
|Additional Information :||© The Electrochemical Society, Inc. 2009. All rights reserved. Except as provided under U.S. copyright law, this work may not be reproduced, resold, distributed, or modified without the express permission of The Electrochemical Society (ECS). The archival version of this work was published in ECS Transactions 22(1)2009.|
|Depositing User :||Symplectic Elements|
|Date Deposited :||04 Dec 2012 10:18|
|Last Modified :||23 Sep 2013 19:43|
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