University of Surrey

Test tubes in the lab Research in the ATI Dance Research

Formal verification of fault-tolerant software design: the CSP approach

Yeung, WL and Schneider, SA (2005) Formal verification of fault-tolerant software design: the CSP approach MICROPROCESSORS AND MICROSYSTEMS, 29 (5). 197 - 209. ISSN 0141-9331

Available under License : See the attached licence file.

Download (311Kb)
[img] Plain Text (licence)

Download (1516b)


Software design techniques for tolerating both hardware and software faults have been developed over the past few decades. Paradoxically, it is essential that fault-tolerant software is designed with the highest possible rigour to prevent faults in itself. Such rigour is provided by formal methods and aided by model checking. We illustrate an approach to fault-tolerant software design based on communicating sequential processes through a running example.

Item Type: Article
Uncontrolled Keywords: Science & Technology, Technology, Computer Science, Hardware & Architecture, Computer Science, Theory & Methods, Engineering, Electrical & Electronic, Computer Science, Engineering, fault tolerance, formal verification, model checking, software design, RECOVERY BLOCKS, SPECIFICATION
Related URLs:
Divisions: Faculty of Engineering and Physical Sciences > Computing Science
Depositing User: Mr Adam Field
Date Deposited: 24 Oct 2011 08:55
Last Modified: 23 Sep 2013 18:45

Actions (login required)

View Item View Item


Downloads per month over past year

Information about this web site

© The University of Surrey, Guildford, Surrey, GU2 7XH, United Kingdom.
+44 (0)1483 300800