Field plate optimization in low-power high-gain source-gated transistors
Sporea, RA, Shannon, JM, Silva, SRP, Trainor, MJ and Young, ND (2012) Field plate optimization in low-power high-gain source-gated transistors IEEE Transactions on Electron Devices, 59 (8). 2180 - 2186. ISSN 0018-9383
Available under License : See the attached licence file.
Official URL: http://dx.doi.org/10.1109/TED.2012.2198823
Source-gated transistors (SGTs) have potentially very high output impedance and low saturation voltages, which make them ideal as building blocks for high-performance analog circuits fabricated in thin-film technologies. The quality of saturation is greatly influenced by the design of the field-relief structure incorporated into the source electrode. Starting from measurements on self-aligned polysilicon structures, we show through numerical simulations how the field plate (FP) design can be improved. A simple source FP around 1 μm long situated several tens of nanometers above the semiconductor can increase the low-voltage intrinsic gain by more than two orders of magnitude and offers adequate tolerance to process variations in a moderately scaled thin-film SGT. © 2012 IEEE.
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|Divisions:||Faculty of Engineering and Physical Sciences > Electronic Engineering > Advanced Technology Institute > Nano-Electronics Centre|
|Deposited By:||Symplectic Elements|
|Deposited On:||23 Oct 2012 10:34|
|Last Modified:||16 Feb 2013 15:11|
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