Field plate optimization in low-power high-gain source-gated transistors

Sporea, RA, Shannon, JM, Silva, SRP, Trainor, MJ and Young, ND (2012) Field plate optimization in low-power high-gain source-gated transistors IEEE Transactions on Electron Devices, 59 (8). pp. 2180-2186.

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Abstract

Source-gated transistors (SGTs) have potentially very high output impedance and low saturation voltages, which make them ideal as building blocks for high-performance analog circuits fabricated in thin-film technologies. The quality of saturation is greatly influenced by the design of the field-relief structure incorporated into the source electrode. Starting from measurements on self-aligned polysilicon structures, we show through numerical simulations how the field plate (FP) design can be improved. A simple source FP around 1 μm long situated several tens of nanometers above the semiconductor can increase the low-voltage intrinsic gain by more than two orders of magnitude and offers adequate tolerance to process variations in a moderately scaled thin-film SGT. © 2012 IEEE.

Item Type:	Article
Divisions :	Faculty of Engineering and Physical Sciences > Electronic Engineering > Advanced Technology Institute > Nano-Electronics Centre
Authors :	Name Email ORCID Sporea, RA Shannon, JM Silva, SRP Trainor, MJ Young, ND
Date :	2012
Identification Number :	10.1109/TED.2012.2198823
Additional Information :	Copyright 2012 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Depositing User :	Symplectic Elements
Date Deposited :	23 Oct 2012 09:34
Last Modified :	31 Oct 2017 14:43
URI:	http://epubs.surrey.ac.uk/id/eprint/721638

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