Field plate optimization in low-power high-gain source-gated transistors
Sporea, RA, Trainor, MJ, Young, ND, Shannon, JM and Silva, SRP (2012) Field plate optimization in low-power high-gain source-gated transistors IEEE Transactions on Electron Devices, 59 (8). ISSN 0018-9383
TED Field Plate Sporea - Revised.pdf - Accepted Version
Available under License : See the attached licence file.
Source-gated transistors (SGTs) have potentially very high output impedance and low saturation voltages, which make them ideal as building blocks for high performance analog circuits fabricated in thin-film technologies. The quality of the saturation is greatly influenced by the design of the field-relief structure incorporated into the source electrode. Starting from measurements on self-aligned polysilicon structures, we show through numerical simulations how the field plate design can be improved. A simple source field plate around 1µm long situated several tens of nm above the semiconductor can increase the low-voltage intrinsic gain by more than two orders of magnitude and offers adequate tolerance to process variations in a moderately scaled thin-film SGT.
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|Divisions:||Faculty of Engineering and Physical Sciences > Electronic Engineering > Advanced Technology Institute > Nano-Electronics Centre|
|Depositing User:||Symplectic Elements|
|Date Deposited:||02 Oct 2012 08:24|
|Last Modified:||23 Sep 2013 19:29|
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