Formal verification of fault-tolerant software design: the CSP approach
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Yeung, WL and Schneider, SA (2005) Formal verification of fault-tolerant software design: the CSP approach MICROPROCESS MICROSY, 29 (5). 197 - 209. ISSN 0141-9331
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Abstract
Software design techniques for tolerating both hardware and software faults have been developed over the past few decades. Paradoxically, it is essential that fault-tolerant software is designed with the highest possible rigour to prevent faults in itself. Such rigour is provided by formal methods and aided by model checking. We illustrate an approach to fault-tolerant software design based on communicating sequential processes through a running example.
| Item Type: | Article |
|---|---|
| Additional Information: | This is an author-prepared version of an article published in Microprocessors and Microsystems, 29, 197-209. © 2005 Elsevier Inc. All rights reserved. Click here to access the published version. |
| Uncontrolled Keywords: | fault tolerance, formal verification, model checking, software design, RECOVERY BLOCKS, SPECIFICATION |
| Divisions: | Faculty of Engineering and Physical Sciences > Computing Science |
| ID Code: | 1940 |
| Deposited By: | Mr Adam Field |
| Deposited On: | 27 May 2010 15:46 |
| Last Modified: | 26 Sep 2012 14:37 |
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