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Formal verification of fault-tolerant software design: the CSP approach

Yeung, WL and Schneider, SA (2005) Formal verification of fault-tolerant software design: the CSP approach MICROPROCESS MICROSY, 29 (5). pp. 197-209.


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Software design techniques for tolerating both hardware and software faults have been developed over the past few decades. Paradoxically, it is essential that fault-tolerant software is designed with the highest possible rigour to prevent faults in itself. Such rigour is provided by formal methods and aided by model checking. We illustrate an approach to fault-tolerant software design based on communicating sequential processes through a running example.

Item Type: Article
Divisions : Faculty of Engineering and Physical Sciences > Computer Science
Authors :
Yeung, WL
Date : 1 June 2005
DOI : 10.1016/j.micpro.2004.07.005
Uncontrolled Keywords : fault tolerance, formal verification, model checking, software design, RECOVERY BLOCKS, SPECIFICATION
Additional Information : This is an author-prepared version of an article published in Microprocessors and Microsystems, 29, 197-209. © 2005 Elsevier Inc. All rights reserved. Click here to access the published version.
Depositing User : Mr Adam Field
Date Deposited : 27 May 2010 14:46
Last Modified : 06 Jul 2019 05:07

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