University of Surrey

Test tubes in the lab Research in the ATI Dance Research

Modeling of High-Current Source-Gated Transistors in Amorphous Silicon

Balon, F, Shannon, J M and Sealy, B J (2005) Modeling of High-Current Source-Gated Transistors in Amorphous Silicon Applied Physics Letters, 86 (7).

[img]
Preview
PDF
fulltext.pdf

Download (86kB)

Abstract

Compared with the field-effect transistor, the source-gated transistor has a much lower saturation voltage and higher output impedance. These features are investigated using computer modeling for amorphous silicon transistors operated at high currents when source barriers are low. In particular, it is shown that low saturation voltages are maintained at high current and are insensitive to source-drain separation. Furthermore, the output impedance is preserved even for submicron source-drain separations.

Item Type: Article
Additional Information:

Published in Applied Physics Letters, Vol. 86, Iss. 7.

Copyright 2005 American Institute of Physics. Click here to access the journal's website.

Divisions: Faculty of Engineering and Physical Sciences > Electronic Engineering > Advanced Technology Institute > Ion Beam Centre
Depositing User: Mr Adam Field
Date Deposited: 27 May 2010 14:05
Last Modified: 23 Sep 2013 18:25
URI: http://epubs.surrey.ac.uk/id/eprint/12

Actions (login required)

View Item View Item

Downloads

Downloads per month over past year


Information about this web site

© The University of Surrey, Guildford, Surrey, GU2 7XH, United Kingdom.
+44 (0)1483 300800